India’s Journey to RISC-V Mastery: MoS Chandrasekhar Leads the Way to Chip Design Excellence!
Union Minister of State for Skill Development and Entrepreneurship and Electronics and IT Rajeev Chandrasekhar inaugurated the Nationwide Roadshow on the Digital India RISC-V (DIR-V) programme, which heralded a defining moment in India’s technological development. This collaboration between C-DAC, IEEE India Council and Ministry of Electronics & IT attracted global leaders in RISC-V design.
Highlighting the occasion, Chandrasekhar said, “This is a significant milestone and a huge step forward that we are able to demonstrate to the whole country today not only the broad chip design capabilities, but also the high performance chip design capabilities of the RISC V domain.”
Highlighting the government’s commitment, Chandrasekhar emphasized, “The opportunities created by Prime Minister Narendra Modi’s policies over the last 7 years represent unprecedented success and growth… Our primary focus is to grow the RISC V and DIR V ecosystem.”
Expressing India’s ambition in the technological landscape, he stated, “It is certainly our ambition as a country and hundreds and thousands of engineers in the audience that we dominate and become, if not a global leader, but certainly among the world’s leading nations in deploying and navigating the talents and capacities to create innovations in RISC V and DIR around V chips and systems.”
Acknowledging the growing startup ecosystem, Chandrasekhar highlighted that the DIR V ecosystem has seen many startups such as Ventana Micro Systems, Esperanto Technologies, InCore Semiconductors, Mindgrove Technologies and Morphing Machines. According to him, the program offers a huge opportunity for startups in the Indian design ecosystem to build next-generation chips around RISC V processors and systems around DIR V devices.
Highlighting future application areas, he noted: “While RISC V has always represented an open source and collaborative framework for innovation in semiconductor design and fab design, now that the need for artificial intelligence and machine learning is growing, DIR V will also be able to meet high performance computing and applications in the coming years.”
The goal of the nationwide roadshow is to give 1,500 participants comprehensive insights into DIR-V VEGA processors and their ecosystem. Facilitated by global leaders like Professor Krste Asanovic and Calista Redmond, the hands-on sessions provide opportunities for participants from 15 colleges across India.
